In recent years, with development of science and technology, storage apparatuses and storage techniques have seen significant developments. In particular, as modern society's thirst for information continues to grow, various information processing devices, e.g., personal computers, laptop computers, smart phones and personal digital assistants (PDAs), have become indispensable tools in the daily life of many people. Accordingly, demand for storage apparatuses, e.g., memory devices, has also increased.
Generally, in an information processing device, a data bus of a memory device is coupled to an arbiter, for providing data storage or access via the data bus to a plurality of control devices, such as a central processing unit (CPU), a video processor, an audio processor or other peripheral devices, wherein the arbiter determines to which control device the dominance of the data bus currently belongs.
With the ever-increasing demand for processing devices that support real-time applications, e.g., synchronous media play, image retrieving or recording, and phone communication in multimedia applications, and ever-increasing improvements in the capabilities of CPUs, there is a commensurate requirement for higher transmission rates for memory devices. As an example, double data rate dynamic random access memory (DDR-DRAM) on the market today has a clock frequency up to hundreds of MHz, but even this level of capability is likely to become insufficient in the near future.
Therefore, one main object of the present invention is to provide improvements in memory systems.